On 24 June 2026, OpenAI and Broadcom announced Jalapeno, a custom inference ASIC targeting a 10 gigawatt deployment through 2029, with a tape-out cycle of nine months from design lock. Microsoft was named among deployment partners. The primary source is openai.com/index/openai-broadcom-jalapeno-inference-chip and the CNBC coverage of the same day.
Coverage of the announcement has been generous with implied dollar totals. Some pieces extrapolate from 10 gigawatts of hyperscale AI compute against public spot prices for similar deployments and produce headline numbers in the tens of billions. These extrapolations are not stated by the parties. The register's rule is that a row cites the primary source and that the primary source does not carry a dollar figure. This note follows that rule.
The programme's book, published 2 January 2026 (print; ebook 6 January), argues in the Chokepoint chapter that vertical integration of the AI stack, from chip design through data centre through model, becomes the load-bearing governance surface once the field's leading players internalise their own inference silicon. Jalapeno is that internalisation, announced roughly six months after the book. The convergence claim is not that OpenAI read the book; it is that the structural argument the book made has become the shape of the industry's own decisions.
Nine months from design lock to tape-out on a custom inference ASIC at a modern process node is aggressive. Not impossible, and Broadcom has done it before, but it depends on inheriting proven IP blocks, running silicon-only bug fixes rather than logic changes, and having pre-cleared fab capacity. The number is informative because it fixes the earliest plausible production silicon. It is not informative about whether the 10 gigawatt target is achievable on that schedule; deployment depends on data centre build-out, power procurement, and the rest of the supply chain, none of which the announcement itself addresses.
Jalapeno lives inside the current chokepoint. Broadcom is a US design house; the fabs it uses sit in Taiwan and the US; the EDA tools are US and European. A custom inference ASIC of this scale is, by construction, embedded in the same supply chain the Chips Act 2.0 and the SAFE Chips work is trying to constrain. That embedding is a governance surface, not a workaround. The book's Chokepoint argument treats supply-chain concentration as leverage; Jalapeno is a datapoint for that argument, in either direction.
A named ASIC, a stated schedule, a partner list, and no invented dollar figure. The convergence claim is structural, not causal. The nine-month tape-out fixes a date. The rest is engineering, capacity, and whatever the export regime decides to do about vertical integration on this scale.
From the book Infinite Architects: Intelligence, Recursion, and the Creation of Everything by Michael Darius Eastwood.