Convergence 9: FlexHEG: tamper-proof guarantee processors for AI chips (ARIA-commissioned)

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Michael Darius Eastwood
Michael Darius Eastwood · Independent AI alignment researcher
Published
Michael Darius Eastwood · Research Notes · 3 July 2026 · Part of the Research evidence spine
Michael Darius Eastwood, independent researcher, London: originator of the embedded-correction alignment thesis (manuscript 8 December 2024, SHA-256 anchored: f0d1f38f).
Register entry 9 of 19. Domain: Hardware. Institution: Petrie, Aarne, Ammann, Dalrymple. External date: 2025-04. Measured against: A2 (concurrent with A2). Classification: CONCURRENT.
Primary source: arXiv:2506.15093

What happened

FlexHEG: tamper-proof guarantee processors for AI chips (ARIA-commissioned).

Why it is in the register

FlexHEG, commissioned by ARIA and published April 2025, proposes tamper-proof guarantee processors that monitor AI chips and enforce usage constraints. It is concurrent with the April 2025 manuscript rather than after it, and the register classes it accordingly. The point of including concurrent rows is the same as the Sharma and Chopra row: the register records the field's movement honestly, and simultaneous independent arrival at substrate-level enforcement is itself evidence that the direction is structural.

How to check this entry

Open the primary source above. Confirm the date. Confirm the finding. Then compare it against the manuscript passage or artifact named in the register entry, whose SHA-256 hash is published on the evidence page. Nothing in this article asks for trust; the entry either survives that comparison or it comes off the register, publicly, the way the programme's retracted scaling figure did.

From the book Infinite Architects: Intelligence, Recursion, and the Creation of Everything by Michael Darius Eastwood.

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